The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having sidewall spacers made of an insulating material, which are used at sidewalls of a gate electrode.
With the advancement in performance of semiconductor devices centered on system LSIs and logic LSIs in recent years, there has evolved a technology of forming a field effect transistor (FET) on a semiconductor substrate of SOI (Silicon on Insulator) structure instead of the conventional bulk Si substrate. This is a method for forming an FET on a thin silicon substrate called the SOI layer on an insulating layer (SiO2) formed on a silicon substrate, for example. This method is superior in that junction capacitors are smaller than in the conventional method using a bulk substrate, so that the transistor operation can be made faster and transistors can be isolated more easily. Above all, a fully depleted-mode FET formed on the above-mentioned SOI layer, having a smaller parasite capacitor and a smaller sub-threshold swing (current Id rises at steep gradient) than in the bulk Si substrate, is drawing attention as a device with low power consumption. Further, because the width of a channel depletion layer is decided by the thickness of the SOI layer, this fully depleted-mode FET is effective in uppressing the short channel effect.
To realize a fully-depleted-mode operation of an SOI device having those merits, it is necessary to make the SOI layer thinner as miniaturization of devices progresses. As shown in IEICE (Institute of Electronics, Information and communication Engineers) papers, C-11 vol. J81-C-11, No. 3, pp. 313-319 (1998), as the gate length was scaled down to 0.35 xcexcm, 0.25 xcexcm and 0.18 xcexcm, the thickness of SOI layers is reduced to about 60 nm, 50 nm and 40 nm. In SOI devices of a generation with a gate length of 0.1 xcexcm it is believed that the thickness of the SOI layer is required to be less than 20 nm, and a progressive thinning is expected to continue.
As the parasitic resistances of the source and drain diffused layers in the SOI layer increase due to a progressive thinning of the SOI layer, the current drive capability of the transistor notably decreases. To preclude this problem, attempts have been made to decrease the resistances of the source and drain regions generally by a method of forming silicide, such as TiSix or CoSix, on the diffused layers. Regarding a method of using CoSix, for example, there has been a report, in which in order for a CoSi2 phase with the lowest resistance, out of three reaction products of Co2Si, CoSi and CoSi2, to be formed selectively at desired parts on both sides of a gate electrode on the SOI layer, a CoSi2 silicide can be formed stably by depositing Co with an optimum thickness on the SOI layer by sputtering, and then performing a thermal reaction process (RTA) in two stages consisting of a first RTA process (550xc2x0 C. for 30 seconds) and a second RTA (700xc2x0 C. for 60 seconds), for example (IEEE Electron Device Letters, Vol. 15, No. 9 (1994)).
However, miniaturization has come to be restricted by the fact that as the SOI layer is made thinner, a not enough amount of Si is left, which is to be consumed by reaction with Co. Moreover, the SOI layer is reduced in thickness as it goes through various processes until suicide is formed, and as devices are reduced in size and the SOI layer becomes thinner, the effects of the above-mentioned problems has come to be not negligible.
The progressive thinning of the SOI layer during the production process makes it difficult to form a suicide layer in a stable manner, and sometimes gives rises to defects consisting of voids. After an interlayer insulating film has been deposited, in a process of forming a contact hole through the interlayer insulating film, if a contact hole opens to that portion of the suicide layer which has the voids mentioned above, because, in this case, the contact hole is virtually continuous through the voids of the interlayer insulating film to a BOX (Buried Oxide) layer as an insulating layer under the SOI layer, a conducting metal that fills up the contact hole often penetrates the BOX layer, resulting in a considerable decrease in yield in the fabrication of devices. Therefore, it is an extremely important in the development of miniaturized SOI devices to minimize shaving of the SOI layer. In this specification, that yield which is affected by penetration of the BOX layer is called xe2x80x9cBOX-related yield.xe2x80x9d
One reason for a decrease in the thickness of the SOI layer, which has serious adverse effects, is shaving that occurs in etching sidewall spacers used for the single-drain or the LLD transistor structure, above all else. There has been demand for a technology for forming sidewall spacers with high insulating film/silicon selectivity by such a method as to reduce shaving almost to zero in the production of semiconductor devices.
The present invention has been made with the above problem in the conventional production method of a field effect transistor in mind and has as a first object to provide newfangled and improved production method and etching method of a field effect transistor, which are capable of forming sidewall spacers for the gate electrode of an SOI device under an etching condition of extremely high etch selectivity compared with prior art and minimizing an amount of shaving of the SOI layer.
A second object of the present invention is to provide newfangled and improved production method and etching method of a field effect transistor, which are capable of forming sidewall spacers for the gate electrode of an SOI device under an etching condition of extremely high etch selectivity compared with prior art and minimizing an amount of shaving of the SOI layer, to thereby achieve a stable high current drive capability of the transistor.
A third object of the present invention is to provide newfangled and improved production method and etching method of a field effect transistor, which are capable of forming sidewall spacers for the gate electrode of a SOI device under an etching condition of extremely high etch selectivity compared with prior art and minimizing an amount of shaving of the SOI layer, to thereby realize a high yield.
A fourth object of the present invention is to provide a newfangled and improved manufacturing method of a semiconductor device having a gate on a semiconductor substrate, which is capable of suitably forming sidewall spacers for the gate.
According to a first aspect of the present invention, there is provided a method for manufacturing a semiconductor device that comprises forming a ate electrode on a semiconductor substrate including silicon; forming an insulating film on the semiconductor substrate and the gate electrode; performing a first etching process to remove the insulating film in an amount corresponding to 70%xcx9c90% of the thickness of the insulating film by anisotropic etching to the insulating film; and performing a second etching process to etch the remaining portion of the insulating film under a condition of higher insulating film/silicon selectivity than insulating film/silicon selectivity in the anisotropic etching.
In the foregoing, a preferable mode is one wherein the insulating film is a silicon oxide film.
Also, a preferable mode is one wherein the second etching step is carried out under a condition of silicon oxide/silicon etch selectivity of not less than 500.
Further, a preferable mode is one where the first etching step is carried out using a mixed gas of C4F8 and Ar as a process gas under a condition of a ratio of Ar gas flow rate to a total gas flow rate is not less than 90%.
Further, a preferable mode is one wherein the first etching step is carried out using a mixed gas including O2 as a process gas.
Additionally, a preferable mode is one wherein the above-mentioned mixed gas including O2 is one of a mixed gas of C4F8, O2 and Ar, a mixed gas of CHF3, O2 and Ar, a mixed gas of CHF3, CF4, O2 and Ar, and a mixed gas of CF4, O2 and Ar.
Further, a preferable mode is one wherein the first etching step and the second etching step are carried out in the same etching equipment.
Further, a preferable mode is one wherein the second etching step is carried out using a mixed gas of CHF3 and CO, keeping a total gas flow rate of not less than 300 sccm, and maintaining a total gas pressure at not less than 60 mTorr.
Further, a preferable mode is one wherein the insulating film is a silicon nitride.
Also, a preferable mode is one wherein the second etching step is carried out under a condition of silicon nitride/silicon etch selectivity of not less than 500.
Further, a preferable mode is one wherein the second etching step is carried out using a mixed gas of CHF3, CH2F2, and CO, keeping a pressure of not less than 20 mTorr and not more than 30 mTorr and under a condition of a mixing ratio of CH2F2 to a mixed gas of CHF3 and CH2F2, is not less than 30%.
Further, a preferable mode is one wherein the first etching step is carried out using a mixed gas including O2 as a process gas.
Further, a preferable mode is one wherein the semiconductor substrate is a semiconductor substrate having an insulating layer and a silicon layer formed on the insulating layer, and wherein the gate electrode is formed on the silicon layer.
According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device that comprises forming a gate electrode on a semiconductor substrate having a silicon layer on a surface thereof; forming an insulating film on the semiconductor substrate and the gate electrode; performing a first etching process to remove the insulating film in an amount corresponding to 70%xcx9c90% of the thickness of the insulating film by anisotropic etching to the insulating film; and performing a second etching process to etch the remaining portion of the insulating film to remove an unnecessary portion other than sidewall spacers covering both sides of the gate electrode under a condition of higher insulating film/silicon selectivity than insulating film/silicon selectivity in the anisotropic etching.